Circuit and method for erasing EEPROM memory arrays to prevent over-erased cells

ABSTRACT

The device and process of this invention provide for eliminating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.

BACKGROUND OF THE INVENTION

This invention relates to nonvolatile memory arrays, such aselectrically-erasable, electrically-programmable, read-only-memories(EEPROMS) of the single-transistor type and to eliminating errors thatoccur in reading EEPROM cell arrays having over-erased cells.

In particular, the invention relates to avoiding or eliminating readerrors resulting from over-erasing the floating-gate conductors ofnonvolatile memory arrays. An EEPROM cell is over-erased when anexcessive number of electrons is removed from its floating gate duringan erasing operation. The source-drain path of an over-erased EEPROMcell is conductive with the control gate and the source or drain at thesame electric potential.

EEPROM arrays include floating-gate memory cells arranged in rows andcolumns. The floating gate of a programmed memory cell is charged withelectrons, and the electrons in turn render the source-drain path underthe charged floating gate nonconductive when a chosen wordline selectvoltage is applied to the control gate. The nonconductive state is readas a "zero" bit. The floating gate of a non-programmed cell ispositively charged, is neutrally charged, or is slightly negativelycharged, such that the source-drain path under the non-programmedfloating gate is conductive when the same chosen wordline select voltageis applied to the control gate. The conductive state is read as a "one"bit.

Each column and row of an EEPROM array may contain thousands of cells.The sources of each cell in a column are connected to a bitline(source-column line). The drains of each cell in a column are connectedto a separate bitline (drain-column line). The control gates of eachcell in a row are connected to a wordline. Prior to first programming,or perhaps after erasure by ultraviolet light, the source-drain paths ofthe cells begin to conduct at a uniform control-gate threshold voltageVt because the floating gates are neutrally charged (having neither anexcess of electrons nor a deficiency of electrons). The initial uniformthreshold voltage Vt may be, for example, +2.5 volts between controlgate and source. The initial uniform threshold voltage Vt may beadjusted by appropriately doping the channel regions of the cells duringmanufacture.

After programming, the source-drain paths of the programmed cells havecontrol-gate threshold voltages Vt distributed over a range between +6volts to +9 volts, for example. The distribution of threshold voltagesVt among individual cells is caused by processing variations, includingvariations in the tunnel oxide thicknesses, the areas of tunnelingregions and in the coupling ratios of the control-gate voltages to thefloating gates, as well as variations in the programming voltagesapplied to individual cells.

After electrical erasure of the cells, the threshold voltages Vt of theerased cells may, for example, be distributed

over a range from perhaps +0.5 to 2.5 volts with the majority of thecells having erased threshold voltages Vt near +1.5 volts, the rangedepending on the localized variations in the tunnel oxide thickness, theareas of tunneling regions, the capacitive coupling ratios betweenwordlines and floating gates, and the strengths of the erasing pulses.Using a lower-strength erasing pulses, the range may be from perhaps+1.5 to +3.5 volts with the majority of the cells having erasedthreshold voltages Vt near 2.5 volts. With higher-strength erasingpulses applied, the distribution may range from perhaps -0.5 to +1.5volts with the majority of cells having erased threshold voltages Vtnear +0.5 volt. Cells with erased threshold voltages Vt less than thatset during the manufacturing process have deficiencies of electrons (orhave net positive charges) on the floating gates. The excess of positivecharges on the floating gates causes the channel regions under suchgates to be enhanced with electrons.

In general, the extent of channel doping, the programming pulsestrength, the erasing pulse strength and other factors are chosen suchthat the source-drain path of a cell will either be conductive ornon-conductive when applying a chosen wordline select voltage to thecontrol gate. The select voltage must have a value somewhere between thehighest erased-threshold-voltage value of erased cells and the lowestprogrammed-threshold-voltage value of the programmed cells. In manymemory arrays, the channel doping, programming/erasing voltages andother factors are chosen such that the wordline select voltage is equalto the available chip supply voltage Vcc, which may be +5 volts. With +5volt applied to the control gate, the source-drain paths of all of theproperly erased cells are conductive only if those cells have thresholdvoltages Vt below the +5 volt select voltage. Similarly, thesource-drain paths of all of the properly programmed cells arenon-conductive only if those cells have threshold voltages Vt greaterthan the +5 volt select voltage. To guarantee that the correct state ofa cell is sensed with a reasonable speed, even with a noisy chip supplyvoltage Vcc and with other typical fluctuations in drain bitlinevoltage, all of the threshold voltages Vt of erased cells should beconsiderably less than +5 volts, perhaps less than +3.5 volts, and allof the threshold voltages Vt of programmed cells should be considerablygreater than +5 volts, perhaps greater than +6.0 volts.

One of the problems associated with EEPROMs of the type without splitgates is the difficulty of reading memory arrays after some of the cellshave been over-erased, becoming depletion-mode devices. Because thechannel regions of the over-erased cells are in connected in parallelwith all of the source-drain paths of other cells in a column,inaccuracies during reading operation may occur where the stored data inthose columns is short-circuited by the over-erased cells. At least someof the over-erased cells may be conductive because the excessivepositive charge on the floating gates causes the channel regions toinvert from P-type to N-type.

The problems of over-erasure may be avoided by constructing cells withpass gates, or split gates, in which the channel between source anddrain comprises two series sections, one section having the control gateseparated from the channel region by the gate dielectric, the secondregion having the floating gate separated from the channel region by thegate dielectric. However, such memory cells require more area on asilicon chip than do cells without split gates.

The problem of over-erasure may also be minimized by performing multipleerasing operations, each operation increasing the erasing energy appliedto the floating gate. Between each operation, the threshold voltages Vtof all of the cells may be checked to see that a given maximum thresholdvoltage Vt is not exceeded. However, that procedure does not providecorrection for any cells that may be over-erased.

Alternatively, a similar procedure may be used to check betweenincreased-energy erasing pulses to determine that the minimum erasedthreshold voltage Vt does not become less than some value greater thanzero. However, this does not always guarantee that the highest erasedthreshold voltage Vt is low enough and, therefore, some of the cells mayremain programmed. The highest erased threshold voltage Vt willdetermine the speed at which the memory will operate.

The circuit and method of U.S. Patent Application Ser. No. 07/367,597,filed June 19, 1989, and also assigned to Texas InstrumentsIncorporated, relate to normal erasure of the cells of a memory arrayfollowed by application of relatively low-energy pre-conditioning pulsesto the cells prior to reprogramming the array. The low-energy pulses maytend to program and/or erase the cells, depending on the which is neededto distribute the threshold voltages between 0 volts and the selectwordline voltage. The circuit and method of U.S. Patent Application Ser.No. 07/509,532, filed Apr. 16, 1990 and also assigned to TexasInstruments Incorporated, relate to erasure of the cells of a memoryarray through alternate application of relatively high-energyprogramming and erasing pulses, followed by alternate application ofalternate programming and erasing pulses with decreasing energy levels.

In the alternative, the negative-voltage method of U.S. PatentApplication Ser. No. 07/437,553, filed Nov. 17, 1989 and also assignedto Texas Instruments Incorporated may be used to eliminate the adverseeffects of over-erasure of memory cells. However, use of a negativevoltage applied to wordlines requires special driver circuitry.

As yet another alternative for eliminating over-erasure errors, thechannel regions of the EEPROM cells may have increased doping and theread voltages may be increased as described in U.S. Patent ApplicationSer. No. 07/437,553, filed Nov. 16, 1989 and also assigned to TexasInstruments Incorporated.

There is a need for an alternative circuit and procedure that permit anEEPROM array to be read without the need for special driver circuitry,while at the same time permitting minimum-size memory cells withoutsplit gates. The circuit and procedure should eliminate errors caused bycells with excessively high or low threshold voltages Vt caused byconventional erasing methods.

SUMMARY OF THE INVENTION

The circuit and process of this invention provide for eliminatingreading errors caused by over-erased cells by applying flash-erasingpulses between the control gates and the source/drain regions of all ofthe cells of an EEPROM array, the flash-erasing pulses having sufficientenergy to cause all of the cells of the array to be over-erased.Subsequently, flash-programming pulses are applied between the controlgates and biased source/drain regions of all of the cells, theflash-programming pulses applied to the control gates have the sameenergy level as programming pulses used to program individual cells.However, the source/drain regions of the cells are biased at a voltagelevel that limits the charge transfer to the floating gates of the cellssuch that, after the flash-programming operation, the cells have a rangeof positive threshold voltages Vt below the select voltage used for readoperations.

The circuit and process of this invention do not require that thethreshold voltages Vt of the cells be monitored during the erasesequence of erase/program operations.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features of this invention are set forth in the appendedclaims. The invention, its features, and its advantages are describedbelow in conjunction with the following drawings:

FIG. 1 is a representation of an array of memory cells and associatedcircuitry according to this invention.

FIG. 2(a) illustrates an example distribution of threshold voltages ofan array of memory cells after manufacture or after ultraviolet-type oferasure and before programming and illustrates an example distributionof threshold voltages after programming.

FIG. 2(b) illustrates example distributions of threshold voltages of thearray of memory cells after erasure.

FIG. 2(c) illustrates example distributions of threshold voltages of anarray of memory cells of this invention after being erased by aflash-erasing operation at relatively high-energy-level and after aflash-programming operation at relatively low energy-level

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT

Referring to FIG. 1, an example array of memory cells, which is anintegral part of a memory chip, is shown for the purpose of illustratinguse of the circuit of this invention. Each cell is a floating-gatetransistor 10 having a source 11, a drain 12, a floating gate 13 and acontrol gate 14. A control terminal of each of the control gates 14 in arow of cells 10 is connected to a wordline 15, and each of the wordlines15 is connected to a wordline decoder 16. A source terminal of each ofthe sources 11 in a column of cells 10 is connected to a source-columnline 17, and each of the source-column lines 17 is connected lo a columndecoder 18. A drain terminal of each of the drains 12 in a column ofcells 10 is connected to a drain-column line 19, and each of thedrain-column lines 19 is connected to the column decoder 18.

In a write or program mode, the wordline decoder 16 may function, inresponse to wordline address signals on lines 20r and to a signal fromread/write control circuit 21, to place a preselected first programmingvoltage Vpp (approx. +16 to +18 volts) on a selected wordline 15,including a selected control gate conductor 14. Column decoder 18, inresponse to signals on lines 20d and to a signal from read/write controlcircuit 21, may function to place a preselected second programmingvoltage (reference potential Vss or ground, or a non-positive voltage)on selected source-column line 17, which includes a selected source 11region. The preselected second programming voltage Vss must differsufficiently from the first preselected programming voltage Vpp thatexcess electrons will migrate, perhaps by Fowler-Nordheim tunneling, tothe selected floating-gate conductor 13 and, as a result, program thatselected floating-gate conductor 13. Column decoder 18 may optionally,in response to signals on lines 20d and to a signal from read/writecontrol 21, place a third preselected voltage Vhs (approx. +7 voltsabove Vss) on deselected source-column lines 17, including deselectedsource 11 regions within the array, to prevent a disturb of programmedfloating-gate conductors associated with the deselected source 11regions. The wordline decoder 16 may optionally, in response to wordlineaddress signals on lines 20r and to a signal from read/write control 21,place a fourth preselected voltage, which may also be Vhs (approx. +7volts), on deselected wordlines 15, including deselected control-gateconductors 14. The fourth preselected voltage should be sufficientlyclose to the second programming voltage that the floating-gateconductors 13 associated with the deselected wordlines 15 will not beprogrammed as a result, but should be sufficiently high that stress willbe reduced across any tunneling windows of cells 10 in deselectedwordlines 15, thereby avoiding de-programming of pre-programmed cells10. The third and fourth preselected voltages should be placed on therespective electrodes before both first and second preselectedprogramming voltages Vpp and Vss are both placed on their respectiveelectrodes. The first programming voltage Vpp may be placed on thecontrol-gate conductors 14 in a gradual manner so as to reducevoltage-induced stress on the selected cell 10. The drain-column lines19 may be left floating. The floating gate 13 of the selected cell 10 ischarged with electrons during programming, and the electrons in turnrender the source-drain path under the floating gate 13 of the selectedcell 10 non-conductive, a state which is read as a "zero" bit.Deselected cells 10 have source-drain paths under the floating gate 13that remain conductive, and those cells 10 are read as "one" bits.

During a prior-art-type flash-erase mode, the column decoder 18functions to apply a positive voltage Vcc (approx. +5 volts) to all thesource-column lines 17. The column decoder 18 functions to leave alldrain-column lines 19 floating. The wordline decoder 16 functions toapply a high negative voltage Vee (approx. -11 volts) to all thewordlines 15. The excess electrons are removed from the floating gates13 of programmed cells 10. Selective erasing may be accomplished bychanging Vee to perhaps -5 volts and by applying voltage Vcc to theselected wordline 15 while perhaps +10 volts is applied to thedeselected wordlines 15 and the selected source-column line 17. Groundor reference voltage Vss is applied to the deselected source-columnlines 17. Other applied voltages are the same as those of theflash-erase example.

In the read mode, the wordline decoder 16 functions, in response towordline address signals on lines 20r and to a signal from read/writecontrol circuit 21, to apply a preselected positive voltage Vcc (approx.+3 to +5 volts) to the selected wordline 15 (and the selected controlgate 14), and to apply a low voltage (ground or Vss) to deselectedwordlines 15. The column decoder 18 functions, in response to columnaddress signals on lines 20d, to apply a preselected positive voltageVsen (approx. +1 to +1.5 volts) to the selected drain-column line 19.The column decoder 18 also functions to connect all source-column lines17 to ground (or Vss). The conductive or nonconductive state of the cell10 connected to the selected drain-column line 19 and the selectedwordline 15 is detected by a sense amplifier (not shown) connected tothe DATA OUT terminal.

As is well-known, the source 11 regions and the drain 12 regions of thememory cells 10 may be interchanged for the various modes of operation.For example, Fowler-Nordheim tunneling for programming and/or erasingmay take place between a drain 12 region and a floating-gate conductor13, or between a source 11 region and a floating-gate conductor 13.Voltages applied to the source 11 and drain 12 regions in the readexample above are interchangeable. Therefore, the terms "source" and"drain" as used herein are considered interchangeable for each mode ofoperation.

For convenience, a table of read, write and prior-art erase voltages isgiven in the TABLE I below:

                  TABLE 1    ______________________________________                          Erase               Read   Write     Selected                                        Flash    ______________________________________    Selected Wordline                 3-5 V    16-18 V   -5 V  -11 V    Deselected Wordlines                 0 V      7 V       10 V  (None)    Selected Source Line                 0 V      0 V       10 V  5 V    Deselected Source Lines                 Float    7 V       0 V   (None)    Drain Lines  1-1.5 V  Float     Float Float    ______________________________________

The cells 10 of FIG. 1 are presumed to be of the type that does notinclude a split gate, or a pass gate. The cells 10 of FIG. 1 are shownconnected with separate source-column lines 17 for each column ofsources 11 and with separate drain-column lines 19 for each column ofdrains 12, although this invention applies equally to cells 10 that arearranged in columns having common bitlines 17 and/or 19.

The source-drain paths of each cell 10 in a column are connected inparallel. Because of the parallel connection, a conductive cell 10 in acolumn will short-circuit all of the other cells 10 in that column. Inparticular, if one of the cells 10 in a column is sufficientlyover-erased, the channel region of that cell 10 will be inverted fromP-type to N-type material by positive charges on floating gate 13, andthe source-drain path of cell 10 will be conductive. A column of cells10 that is short-circuited by one or more over-erased cells 10 isdifficult, perhaps impossible, to read if the cell 10 is constructedwithout a pass gate.

Application of pulsed programming voltages or currents to selected cells10 causes pulsed programming electric fields in the insulated regionbetween the floating gate 13 and the substrate of the selected memorycells 10 of the EEPROM array, the electric fields being adjacent atleast an area of floating gate 13 and being directed away from that areaof each of the floating gates 13. As illustrated by curve A of FIG.2(a), the cells 10 of an array have, in general, a fairly uniforminitial threshold voltage Vts prior to programming of those cells 10.The initial threshold voltage Vts is set during manufacture by dopingthe channel region of the cell 10 with an impurity of conductivity-type(P-type or N-type), usually opposite that used to dope the source 11 anddrain 12 regions. The initial threshold voltage Vts infloating-gate-type memory cells 10 is usually in the range of one halfof the wordline-select voltage Vcc applied to the control gate duringread operations. The wordline select voltage Vcc is often the chipsupply voltage. For example, initial threshold voltages Vt of availablecells 10 may range from +1.5 to +3.5 volts where Vcc is 5 volts.

After application of pulsed programming voltages/currents, asillustrated by curve B of FIG. 2(a), selected cells 10 have distributedthreshold voltages Vt above a minimum programmed-threshold voltage Vtp,the distribution being caused by random processing variations. The valueof Vtp in may be, for example, one volt above wordline select voltageVcc (one volt above the supply voltage). Some of the cells 10 may havelocalized thinner dielectrics, perhaps resulting from a process that islocation-dependent. Other cells 10 may have smaller-area channelregions, perhaps because of variations in masking size. The programmedthreshold voltage Vt distribution B is illustrated as a Gaussian orbell-shaped distribution in FIG. 2(a), although actual distributionshave a variety of shapes depending on particular types of processingvariations.

Curve C of FIG. 2(b) illustrates an erased threshold voltage Vtdistribution in which, according to known procedures, the cells 10 aretested between application of pulsed erasing voltages/currents ofdifferent energy levels until all of the cells 10 have thresholdvoltages Vt below a prescribed maximum threshold voltage Vtmax, which isless than the select voltage Vcc. As illustrated by the negativethreshold voltages Vt of Curve C, a disadvantage of the known method isthat some of the cells 10 may be over-erased in order to achieve themaximum threshold voltage limitation, Vtmax. Those over-erased cells 10will short-circuit the connected source-column and drain-column lines 17and 19, causing erroneous reading of the programmed cells 10 sharing thecolumns in which over-erased cells 10 are located.

Curve D of FIG. 2(b) illustrates a type of erased threshold voltage Vtdistribution in which cells 10 are tested between application of pulsederasing voltages/currents of different energy levels until all of thecells 10 have threshold voltages Vt above a prescribed minimum thresholdvoltage Vtmin. As illustrated by Curve D, a disadvantage of this methodis that some of the cells 10 may have threshold voltages Vt that exceedthe select voltage Vcc. Those cells 10 will be read as programmed cells.

Curve E of FIG. 2(b) illustrates an extreme type of erased thresholdvoltage Vt distribution in which some of the cells 10 are over-erasedand in which some of the cells 10 remain programmed.

In accordance with this invention the cells 10 are prepared forindividual programming by subjecting the array to a flash-eraseoperation, then a flash-program operation. Column decoder 18 andwordline decoder 16, in response to signals from erase control circuit22 cause the cells 10 to be flash-erased, then and flash-programmed.Erase control circuit 22 causes pulsed electric fields adjacent asurface of each of the floating gates of the memory cells 10 of theEEPROM array, the electric fields directed toward or away from thatsurface of each floating gate. Erase control circuit 22 initially causesrelatively high-energy-level erasing pulsed electric fields adjacenteach floating gate 13. Then erase control circuit 22 causes relativelylow-energy programming pulsed electric fields adjacent each floatinggate 13. The pulsed voltage applied to the control gates 14 of the cells10 is equal to the same programming voltage Vpp used to programindividual cells 10. However, erase control circuit 22 causes a biasvoltage Vbb so be applied to the sources 11, or the drains 12, of thecells 10. The voltage Vbb decreases the voltage between the floatinggate and the source 11/drain 12, thereby decreasing the energy-level ofthe pulsed flash programming electric field and, therefore, decreasingthe amount of charge transferred between the floating gate 13 and thesource 11/drain 12 during application of the flash-programming voltages.By properly selecting Vbb, each cell 10 will have a positive thresholdvoltage Vt that has the same polarity as the predetermined wordlineselect voltage (which may be Vcc), or read voltage and that is less thanthat read voltage. An example distribution of the threshold voltages Vtafter the flash-erasing operation is shown as bell-shaped curve F inFIG. 2(c). An example distribution of the threshold voltages Vt afterthe subsequent flash-programming operation is shown bell-shaped curves Gin FIG. 2(c). The actual distributions will not necessarily have thatshape.

If tunnel-erase-type memory cells 10 are designed to be flash-erased,but not over-erased, using erasing voltages in the range of 10 to 15volts as in the TABLE I above, then erasing pulses in the range of 16 to22 volts, for example, should be used to over-erase the cells 10 inaccordance with this invention, assuming that the pulse length of thevoltages is the same in both cases. If the voltage of the electricalenergy pulses normally used to tunnel-program individual cells 10 or thearray is in the range of 15 to 20 volts, the bias voltage Vbb may be,for example, in the range of 3 to 4 volts, assuming again that the pulselength of the voltages is the same in both cases.

As is also well-known, a fraction of the electrical pulse energy appliedbetween each control gate 14 of and each source 11 or drain 12 of cells10 is coupled to the floating gates 13.

The relative energy levels of the erasing sequence pulses may becontrolled by current-limiting circuitry, by impulse-length-timingcircuitry, or by other means of controlling energy-related product ofvoltage, current and time. Such circuitry is well-known in the art. Forexample, if the pulse lengths of the electrical programming and erasingpulses remain the same during the erasing sequence, the product of thevoltage and current may be controlled to decrease the pulse energieswith each program/erase cycle. Similarly, if the voltage or current ofthe electrical programming and erasing pulses remain the same during theerasing sequence, the length of the electric pulses may be shortened todecrease the pulse energies with each program/erase cycle. In fact, therelative energy levels of the pulses may be decreased by controlling theproduct of pulse voltage, pulse current and pulse length to decrease thepulse energies with each flash-program/flash-erase cycle.

After the cells 10 have been erased according to this invention,individual cells 10 may be programmed. The threshold voltages Vt of theprogrammed cells 10 will again be distributed over a range such as thatillustrated by curve B of FIG. 2(a).

While the examples shown in this description relate to cell 10structures using Fowler-Nordheim tunneling for programming, the conceptis equally valid for cell 10 structures using channel-hot-electron orsimilar-type programming. In fact, the concept of this invention isapplicable to all known nonvolatile memory arrays having floating-gatecells 10 that are programmable and erasable using electric field pulses.

Use of the circuit and procedure of this invention is straightforward.The type of cell structure and the charging/discharging structure forthe floating gate must be chosen. The insulator, oxide or other type, toisolate the surfaces of the floating gate from other conducting surfacesmust be chosen. If a tunneling-type structure is used for chargingand/or discharging the floating gate, then sufficient voltage must beapplied across the tunnel to cause the oxide or other insulator tobreakdown. The voltage across the tunnel may be a fraction of thevoltage applied between the control electrode and the source/drain path.The fraction at the start of the pulse may be determined fromcapacitance ratios. The breakdown will occur at a point where theelectric field strength is highest. The relationship between voltageapplied to a control electrode and the highest electric field maysometimes be calculated or derived from a handbook, may sometimes befound in literature (e.g., textured oxide surfaces), and may sometimesbe derived from test structures. If hot-carrier programming and/orerasing is used, similar procedures apply to design of the structure andcircuitry. Whether using tunneling, hot-carrier, or any other method, atest-cell structure may be formed on an integrated circuit chip prior tofinal design of programming and erasing circuitry, the cell structuretested on that chip using probes to determine the programming anderasing voltages necessary for operation, the circuitry then designed toprovide those voltages for the manufactured memory array.

For example, nine floating-gate-type memory cells 10 with tunnelingwindows on the source 11 side were found to have manufactured voltagethresholds ranging from 1.01 volts to 1.07 volts. The nine cells 10 wereon a test substrate and, using probes, were over-erased to have the samethreshold voltages Vt of -8.30 volts. The cells 10 were then programmedwith the source 11 biased at 4 volts, resulting in threshold voltages Vtranging from 0.76 volts to 1.39 volts, well below the read voltage of3.0 volts. The cells 10 were subsequently programmed without the biasvoltage, resulting in threshold voltages ranging from 3.94 volts to 5.03volts, well above the read voltage of 3.0 volts.

As is well-known, the programming and erasing pulses may be ramped tominimize damage to the floating gate insulation.

While this invention has been described with respect to an illustrativeembodiment, this description is not intended to be construed in alimiting sense. Upon reference to this description, variousmodifications of the illustrative embodiment, as well as otherembodiments of the invention, will be apparent to persons skilled in theart. It is contemplated that the appended claims will cover any suchmodifications or embodiments that fall within the scope of theinvention.

I claim:
 1. A method for erasing a memory cell having at least onecontrol terminal, a floating gate, a source terminal and a drainterminal, said memory cell programmable and erasable by applyingelectrical energy between said control terminal and at least one of saidsource and drain terminals to cause programming and erasing pulsedelectric fields adjacent said floating gate, said memory cell readableusing a preselected read voltage applied between said control terminaland at least one of said source terminal and said drain terminal, themethod comprising:initially applying an erasing electrical energy pulsehaving a first energy-level between said control terminal and said atleast one of said source and drain terminals of said cell; and thenapplying a programing electrical energy pulse having a secondenergy-level between said control terminal and said at least one of saidsource and drain terminals of said cell; wherein said first energy levelof said erasing electrical energy pulse is sufficient to cause said cellto have a threshold voltage of opposite polarity to said preselectedread voltage; and wherein said second energy level of said programmingelectrical energy pulse is such that said cell has a threshold voltageof the same polarity as said read voltage but that is less than saidread voltage.
 2. The method of claim 1, wherein said programmingelectrical energy pulse causes a pulsed electric field directed awayfrom said floating gate, and wherein said erasing electrical energypulse causes a pulsed electric field directed toward said floating gate.3. The method of claim 1, wherein said control terminal is connected toa wordline, wherein said source terminal is connected to a source-columnline, wherein said drain terminal is connected to a drain-column line,and wherein said programming and erasing electrical energy pulses arecaused by pulsed programming voltages and pulsed erasing voltagesapplied between said wordline and at least one of said source-columnline and said drain-column line.
 4. The method of claim 1, wherein saidcontrol terminal is connected to a wordline, wherein said sourceterminal is connected to a source-column line, wherein said drainterminal is connected to a drain-column line, wherein said programmingand erasing electrical energy pulses are caused by pulsed programmingvoltages and pulsed erasing voltages applied between said wordline andat least one of said source-column line and said drain-column line; andwherein said second energy-level of said programming electrical energypulse is controlled by applying a bias voltage to at least one of a saidsource-column line or a said drain-column line.
 5. The method of claim1, wherein said control terminal is connected to a wordline, whereinsaid source terminal is connected to a source-column line, wherein saiddrain terminal is connected to a drain-column line, wherein said secondand first energy-levels of said programming and erasing electricalenergy pulses are caused by pulsed programming currents and pulsederasing currents applied between said wordline and at least one of saidsource-column line and said drain-column line.
 6. The method of claim 1,wherein said control terminal is connected to a wordline, wherein saidsource terminal is connected to a source-column line, wherein said drainterminal is connected to a drain-column line, wherein said second andfirst energy-levels of said programming and erasing electrical energypulses are related to the length of electrical programming and erasingpulses applied between said wordline and at least one of saidsource-column line and said drain-column line.
 7. A non-volatile memoryarray, comprising:memory cells arranged in rows and columns, each saidmemory cell having a source-drain path between first and secondterminals and having a control-gate terminal; a source-column lineconnected to each said first terminal of each said memory cell in a saidcolumn; a drain-column line connected to each said second terminal ofeach said memory cell in a said column; a wordline connected to eachsaid control-gate terminal of each said memory cell in a said row; eachsaid memory cell having a floating-gate conductor insulated from saidsource-drain path and from said control gate, said floating-gateconductor being programmable and erasable by programming and erasingelectrical energy pulses applied between said control gate and at leastone of said first and said second terminals; a column decoder connectedto said source-column lines and said drain-column lines and a wordlinedecoder connected to said wordlines for providing said programming anderasing electrical energy pulses to said memory cells via said wordlinesand at least one of said source-column lines and said drain-columnlines; and an erase control circuit for causing said column decoder andsaid wordline decoder to provide said programming and erasing electricalenergy pulses to said memory cells via said wordlines and at least oneof said source-column lines and said drain-column lines, said controlcircuit causing said erasing electrical energy pulses having asufficiently high energy-level to cause .Iadd.at least one of.Iaddend.said floating gates initially to be over-erased, said controlcircuit subsequently causing said column decoder and said wordlinedecoder to provide said programming electrical energy pulses to . .saidcells.!. .Iadd.cell having said at least one of said floating gates.Iaddend.via said wordlines and at least one of said source-column linesand said drain-column lines.Iadd., such that said cell has a positivethreshold voltage less than a predetermined positive wordline selectvoltage.Iaddend..
 8. The array of claim 7, wherein said energy-level ofsaid programming and erasing electrical energy pulses is controlled byvarying voltages applied to said wordlines and at least one of saidsource-column lines and said drain-column lines.
 9. The array of claim7, wherein said column decoder also provides a predetermined biasvoltage to at least one of said source-column lines and drain-columnlines, wherein said erase control circuit also causes said bias voltageto be applied to at least one of said source-column lines and saiddrain-column lines, and wherein said predetermined bias voltage has avalue that causes said cells to have positive threshold voltages lessthan a predetermined positive wordline select voltage.
 10. The array ofclaim 7, wherein said energy-level of said programming and erasingelectrical energy pulses is controlled by varying currents applied tosaid wordlines and at least one of said source-column lines and saiddrain-column lines.
 11. The array of claim 7, wherein said energy-levelof said programming and erasing electrical energy pulses is controlledby varying the length of electrical pulses applied to said wordlines andat least one of said source-column lines and said drain-column lines.12. A method of erasing a memory-cell array prior to programming saidarray, each said memory cell including a floating gate, .Iadd.each saidmemory cell characterized by a positive read voltage, .Iaddend.themethod comprising:initially applying erasing electrical energy pulses tosaid cells of said memory cell array, said erasing electrical energypulses having a energy-level sufficient to cause . .each.!. .Iadd.atleast one said .Iaddend.memory cell of said array to have a negativethreshold voltage; then applying programming electrical energy pulses tosaid cells of said memory cell array, said programming electrical energypulses having an energy-level sufficient to cause . .each.!. .Iadd.saidat least one .Iaddend.cell of said array to have a positive thresholdvoltage .Iadd.less than said read voltage of said array.Iaddend.. 13.The method of claim 12, wherein said array includes a plurality ofwordlines, source-column lines and drain-column lines; wherein each saidmemory cell has a terminal connected to a said wordline, has a terminalconnected to a said source-column line, and has a terminal connected toa said drain-column line; wherein pulsed programming and erasingvoltages are applied between said wordlines of said memory array and atleast one of said source-column lines and said drain-column lines ofsaid memory array electrical energy pulses.
 14. The method of claim 12,wherein said array includes a plurality of wordlines, source-columnlines and drain-column lines; wherein each said memory cell has aterminal connected to a said wordline, has a terminal connected to asaid source-column line, and has a terminal connected to a saiddrain-column line; wherein pulsed programming and erasing currents areapplied between said wordlines of said memory array and at least one ofsaid source-column lines and said drain-column lines of said memoryarray to form said pulsed programming and erasing electrical energypulses.
 15. The method of claim 12, wherein said array includes aplurality of word lines, source-column lines and drain-column lines;wherein each said memory cell has a terminal connected to a saidwordline, has a terminal connected to a said source-column line, and hasa terminal connected to a said drain-column line; whereinvariable-length programming and erasing electric pulses are appliedbetween said wordlines of said memory array and at least one of saidsource-column lines and said drain-column lines of said memory array;and wherein said energy-level of said programming and erasing electricalenergy pulses is related to the length of said variable-lengthprogramming and erasing electric pulses.
 16. The method of claim 12,wherein said erasing electrical energy pulses cause pulsed electricfields directed toward said floating gates and wherein said programmingelectrical energy pulses cause pulsed electric fields directed away fromsaid floating gates. .Iadd.
 17. A method for erasing a memory cellhaving at least one control terminal, a floating gate, a source terminaland a drain terminal, said memory cell programmable and erasable byapplying electrical energy between said control terminal and at leastone of said source and drain terminals to cause programming and erasingpulsed electric fields adjacent said floating gate, said memory cellreadable using a preselected read voltage applied between said controlterminal and at least one of said source terminal and said drainterminal, the method comprising:initially applying an erasing electricalenergy pulse having a first energy-level between said control terminaland said at least one of said source and drain terminals of said cell;and then applying a programming electrical energy pulse having a secondenergy-level between said control terminal and said at least one of saidsource and drain terminals of said cell; wherein said first energy levelof said erasing electrical energy pulse is sufficient to cause said cellto have a threshold voltage less than a first voltage; and wherein saidsecond energy level of said programming electrical energy pulse is suchthat said cell has a threshold voltage greater than said first voltageand less than said read voltage. .Iaddend..Iadd.18. The method of claim17, wherein said first voltage is zero volts. .Iaddend..Iadd.19. Amethod for erasing a memory cell having at least one control terminal, afloating gate, a source terminal and a drain terminal, said memory cellprogrammable and erasable by applying electrical energy between saidcontrol terminal and at least one of said source and drain terminals tocause programming and erasing pulsed electric fields adjacent saidfloating gate, said memory cell readable using a preselected readvoltage applied between said control terminal and at least one of saidsource terminal and said drain terminal, the method comprising:initiallyapplying an erasing electrical energy pulse having a first energy-levelbetween said control terminal and said at least one of said source anddrain terminals of said cell; and then applying a programming electricalenergy pulse having a second energy-level between said control terminaland said at least one of said source and drain terminals of said cell;wherein said first energy level of said erasing electrical energy pulseis sufficient to cause said cell to have a threshold voltagerepresenting a more energetically erased condition than that of a firstvoltage, said first voltage representing an erased condition relative tothe read voltage; and wherein said second energy level of saidprogramming electrical energy pulse is such that said cell has athreshold voltage between said first voltage and said read voltage..Iaddend..Iadd.20. The method of claim 19, wherein said first voltage iszero volts. .Iaddend..Iadd.21. A method of erasing a floating-gatememory cell having a preselected read voltage, comprising the stepsof:erasing the memory cell such that the cell has an initial thresholdvoltage less than a first voltage; and programming the memory cell suchthat the cell has a final threshold voltage greater than the firstvoltage and less than the preselected read voltage. .Iaddend..Iadd.22.The method of claim 21, wherein the first voltage is zero volts..Iaddend..Iadd.23. A method of erasing a floating-gate memory cellhaving a preselected read voltage, comprising the steps of:erasing thememory cell such that the cell has an initial threshold voltagerepresenting a more energetically erased condition than that of a firstvoltage, said first voltage representing an erased condition relative tothe read voltage; and programming the memory cell such that the cell hasa final threshold voltage between the first voltage and the preselectedread voltage. .Iaddend..Iadd.24. The method of claim 23, wherein thefirst voltage is zero volts. .Iaddend..Iadd.25. A memory device readableusing a preselected read voltage, comprising:a source; a drain separatedfrom said source by a source-drain path; a control gate insulated fromsaid source-drain path; a floating gate insulated from said source-drainpath and said control gate; a column decoder coupled to said source anddrain to apply programming and erasing voltages; a wordline decodercoupled to said control gate to apply programming and erasing voltagesto said control gate; and an erase control circuit coupled to saidcolumn decoder and wordline decoder, said control circuit controllingsaid column decoder and wordline decoder initially to generate erasingvoltages sufficient to result in an initial threshold voltage less thana first voltage, and subsequently to generate programming voltagessufficient to result in a final threshold voltage less than the readvoltage. .Iaddend..Iadd.26. The memory device of claim 25, wherein saidfinal threshold voltage resulting from said programming voltages isgreater than said first voltage. .Iaddend..Iadd.27. The memory device ofclaim 26, wherein said first voltage is zero volts. .Iaddend..Iadd.28. Amemory device readable using a preselected read voltage, comprising:asource; a drain separated from said source by a source-drain path; acontrol gate insulated from said source-drain path; a floating gateinsulated from said source-drain path and said control gate, saidfloating-gate being programmable and erasable by programming and erasingelectrical energy pulses applied between said control gate and at leastone of said source and drain; a column decoder connected to said sourceand drain and a wordline decoder connected to said control gate toprovide said programming and erasing electrical energy pulses; and anerase control circuit operable to cause said column decoder and saidwordline decoder to provide said programming and erasing electricalenergy pulses, said control circuit causing said erasing electricalenergy pulses to have a sufficiently high energy-level to result in aninitial threshold voltage less than a first voltage, said controlcircuit subsequently causing said column decoder and said wordlinedecoder to provide said programming electrical energy pulses sufficientto result in a final threshold voltage less than the read voltage..Iaddend..Iadd.29. The memory device of claim 28, wherein said finalthreshold voltage resulting from said programming electrical energypulses is greater than said first voltage. .Iaddend..Iadd.30. The memorydevice of claim 29, wherein said first voltage is zero volts..Iaddend..Iadd.31. A memory device readable using a preselected readvoltage, comprising:a source; a drain separated from said source by asource-drain path; a control gate insulated from said source-drain path;a floating gate insulated from said source-drain path and said controlgate; a first decoder coupled to said source and drain to applyprogramming and erasing voltages; a second decoder coupled to saidcontrol gate to apply programming and erasing voltages to said controlgate; and an erase control circuit coupled to said column decoder andwordline decoder, said control circuit controlling said column decoderand wordline decoder initially to generate erasing voltages sufficientto result in an initial threshold voltage less than a first voltage, andsubsequently to generate programming voltages sufficient to result in afinal threshold voltage greater than said first voltage and less thanthe read voltage. .Iaddend..Iadd.32. The memory device of claim 31,wherein said first voltage is zero volts. .Iaddend.